Разработка процессорного модуля
Дипломная работа - Компьютеры, программирование
Другие дипломы по предмету Компьютеры, программирование
OGIC_VECTOR(8 downto 0);
signal COP, TgB, TgBin: STD_LOGIC;
signal res: STD_LOGIC_VECTOR(15 downto 0);
process(clk,rst)is
begin
if rst='0' then
A'0');
B'0');
C'0');
elsif rising_edge(clk)then
A<=Ain;
B<=Bin;
C<=Cin;
r<=res;
Cnt<=Cntin;
TgB<=TgBin;
end if;
end process;
COP<=d3 when y(3)='1'
else COP;
Ain<=d1 when y(1)='1'
else A;
Bin<=d2 when y(2)='1'
else C(0) & B(7 downto 1) when y(7)='1'
else B;
Cin<="000000000" when y(4)='1'
else C + A(7 downto 0) when y(6)='1'
else "0" & C(8 downto 1) when y(8)='1'
else "0" & C(7) & C(7 downto 1) when y(11)='1'
else C + not(A(7 downto 0)) + 1 when y(12)='1'
else C;
Cntin<=8 when y(5)='1'
else Cnt-1 when y(9)='1'
else Cnt;
res(15 downto 0)<= C(7 downto 0) & B(7 downto 0) when y(13)='1'
else res;
TgBin<= B(0) when y(10)='1'
else TgB;
--Formirovanie priznakov rezultata
x(1)<=COP;
x(2)<='1' when B(0)='1' else '0';
x(3)<='1' when Cnt=0 else '0';
x(4)<='1' when C(8)='1' else '0';
x(5)<='1' when TgB='1' else '0';OA;
ПРИЛОЖЕНИЕ 2
модель управляющего автоматаIEEE;IEEE.STD_LOGIC_1164.all; IEEE.STD_LOGIC_unsigned.all;
YA is
port(
clk, rst : in STD_LOGIC;
x : in STD_LOGIC_VECTOR(5 downto 0);
y : out STD_LOGIC_VECTOR(13 downto 0)
);YA;
YA of YA isTCommand is std_logic_vector(19 downto 0);TROM is array(0 to 11) of TCommand;ROM:TROM := (
-yyyyyyyyyxxxaaaaaaaa
"00101011100100100001",--0
"00000000001001110110",--1
"00000000001001000011",--2
"01000000000001000100",--3
"01110100001100100101",--4
"11000000000000000000",--5
"01000000000001110111",--6
"01111100010010011000",--7
"00010000001100011010",--8
"10000000001100011010",--9
"00000000010101011011",--10
"10100000000001010101"--11
);RegCom:TCommand;TY is array(0 to 6) of INTEGER; Y1: TY :=(0,1,6,7,11,12,13);Y2: TY :=(0,2,8,10,0,0,0);Y3: TY :=(0,3,9,0,0,0,0); Y4: TY :=(0,4,0,0,0,0,0);Y5: TY :=(0,5,0,0,0,0,0);yConv: STD_LOGIC_VECTOR(13 downto 0);
process(rst,clk) is
begin
if rst='0' then
RegCom'0');
elsif rising_edge(clk) then
if x(conv_integer(RegCom(10 downto 8))) ='0' then
RegCom<=ROM(conv_integer(RegCom(7 downto 4)));
else RegCom<=ROM(conv_integer(RegCom(3 downto 0)));
end if;
end if;
end process;
process (RegCom) is
begin
yConv'0');
yConv(Y1(conv_integer(RegCom(19 downto 17))))<='1';
yConv(Y2(conv_integer(RegCom(16 downto 15))))<='1';
yConv(Y3(conv_integer(RegCom(14 downto 13))))<='1';
yConv(Y4(conv_integer(RegCom(12 downto 12))))<='1';
yConv(Y5(conv_integer(RegCom(11 downto 11))))<='1';
end process;
y<=yConv;
architecture YA;
ПРИЛОЖЕНИЕ 3
модель процессорного устройствоIEEE;IEEE.STD_LOGIC_1164.all; IEEE.STD_LOGIC_unsigned.all;
PM is
port(
clk, rst : in STD_LOGIC;
d1 : in STD_LOGIC_VECTOR(7 downto 0);
d2 : in STD_LOGIC_VECTOR(7 downto 0);
d3 : in STD_LOGIC;
r:out STD_LOGIC_VECTOR(15 downto 0)
);PM;
PM of PM isOA is
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(13 downto 0);
d1 : in STD_LOGIC_VECTOR(7 downto 0);
d2 : in STD_LOGIC_VECTOR(7 downto 0);
d3 : in STD_LOGIC;
r:out STD_LOGIC_VECTOR(15 downto 0);
x: out STD_LOGIC_VECTOR(5 downto 0)
);component;
YA is
port(
clk, rst : in STD_LOGIC;
x : in STD_LOGIC_VECTOR(5 downto 0);
y : out STD_LOGIC_VECTOR(13 downto 0)
);component;nclk: std_logic;y: STD_LOGIC_VECTOR (13 downto 0);x: STD_LOGIC_VECTOR (5 downto 0);
nclk<= not clk;
OA_I: OA port map(clk, rst, y(13 downto 0), d1, d2, d3, r, x);
YA_P: YA port map(nclk, rst, x, y);PM;