Розробка цифрових засобiв ПЛРЖС в iнтегрованому середовищi проектування MAX+PLUS II
Дипломная работа - Компьютеры, программирование
Другие дипломы по предмету Компьютеры, программирование
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4- D- (CLK), (Reset). (LOAD) 0 1: 0 , 1 .
10- D- , . 10- тАЬтАЭ (Register_1_input[9..0]), (Enable), (Set), (Clk), (Load) (Register_1_output).
8.3 COM- AHDL MAX+PLUS II
20 10 ( ) AHDL MAX+PLUS II :
Subdesign encipherer_1
(
Encipherer_1_input[20..1] : input;
Encipherer_1_output[10..1] : output;
)
Begin
CASE Encipherer_1_input[] IS
WHEN b"00000000000000000001" => Encipherer_1_output[] = b"0000000011";
WHEN b"00000000000000000010" => Encipherer_1_output[] = b"0000000101";
WHEN b"00000000000000000100" => Encipherer_1_output[] = b"0000000111";
WHEN b"00000000000000001000" => Encipherer_1_output[] = b"0000001001";
WHEN b"00000000000000010000" => Encipherer_1_output[] = b"0000001011";
WHEN b"00000000000000100000" => Encipherer_1_output[] = b"0000001101";
WHEN b"00000000000001000000" => Encipherer_1_output[] = b"0000001111";
WHEN b"00000000000010000000" => Encipherer_1_output[] = b"0000010001";
WHEN b"00000000000100000000" => Encipherer_1_output[] = b"0000010011";
WHEN b"00000000001000000000" => Encipherer_1_output[] = b"0000010101";
WHEN b"00000000010000000000" => Encipherer_1_output[] = b"0000010111";
WHEN b"00000000100000000000" => Encipherer_1_output[] = b"0000011001";
WHEN b"00000001000000000000" => Encipherer_1_output[] = b"0000011011";
WHEN b"00000010000000000000" => Encipherer_1_output[] = b"0000011101";
WHEN b"00000100000000000000" => Encipherer_1_output[] = b"0000011111";
WHEN b"00001000000000000000" => Encipherer_1_output[] = b"0000100001";
WHEN b"00010000000000000000" => Encipherer_1_output[] = b"0000100011";
WHEN b"00100000000000000000" => Encipherer_1_output[] = b"0000100101";
WHEN b"01000000000000000000" => Encipherer_1_output[] = b"0000100111";
WHEN b"10000000000000000000" => Encipherer_1_output[] = b"0000101001";
WHEN OTHERS => Encipherer_1_output[] = b"1111111111";
End CASE;
End;
4 , 2 ( ) AHDL MAX+PLUS II :
Subdesign multiplexer_1
(
Multiplexer_1_input[4..1] : input;
Switch_signal[2..1] : input;
Enable : input;
Multiplexer_1__output : output;
)
Begin
if Enable == 0 then
case Switch_signal[2..1] is
when 0 => Multiplexer_1__output = Multiplexer_1_input[1];
when 1 => Multiplexer_1__output = Multiplexer_1_input[2];
when 2 => Multiplexer_1__output = Multiplexer_1_input[3];
when 3 => Multiplexer_1__output = Multiplexer_1_input[4];
end case;
end if;
End;
10- AHDL MAX+PLUS II