Разработка системы сжатия эхо-сигналов различной длительности
Дипломная работа - Компьютеры, программирование
Другие дипломы по предмету Компьютеры, программирование
--(X_Y_WIDTH + W_SIZE_CD+1+7 downto 0)timer=72 THEN_Re_1(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe1_out;_Im_1(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm1_out;_Re_2(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe2_out;_Im_2(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm2_out;_Re_3(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe3_out;_Im_3(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm3_out;_Re_4(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe4_out;_Im_4(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm4_out;
-_Re_1(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe1_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_1(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm1_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Re_2(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe2_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_2(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm2_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Re_3(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe3_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_3(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm3_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Re_4(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe4_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_4(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm4_out(X_Y_WIDTH + W_SIZE_CD+1+6);
-_Re_1(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe1_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_1(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm1_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Re_2(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe2_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_2(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm2_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Re_3(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe3_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_3(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm3_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Re_4(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe4_out(X_Y_WIDTH + W_SIZE_CD+1+6);_Im_4(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm4_out(X_Y_WIDTH + W_SIZE_CD+1+6);IF;IF;RISING_EDGE (clk_160) THEN --accum summ_Re_1_2<=Acc_Re_1+Acc_Re_2;_Im_1_2<=Acc_Im_1+Acc_Im_2;_Re_3_4<=Acc_Re_3+Acc_Re_4;_Im_3_4<=Acc_Im_3+Acc_Im_4;IF;RISING_EDGE (clk_160) THEN --accum summ_Re<=Sum_Re_1_2+Sum_Re_3_4;_Im<=Sum_Im_1_2+Sum_Im_3_4;IF;PROCESS;_XR<=Sum_Re;_YR<=Sum_Im;_X1<=Acc_Re_1;_Y1<=Acc_Im_1;_X2<=Acc_Re_2;_Y2<=Acc_Im_2;_X3<=Acc_Re_3;_Y3<=Acc_Im_3;_X4<=Acc_Re_4;_Y4<=Acc_Im_4;(clk_160) --shift C_D;process;(CLK_160) -- counter ZRISING_EDGE (CLK_160)THENRES_160 = 1 THEN_Z <= 0;(COUNT_H1 = 1) THEN_Z <= COUNT_Z + 1;_Z <= COUNT_Z;IF;IF;process;(CLK_160) -- counter hRISING_EDGE (CLK_160)THEN_160 <= NRD AND MS(1) AND not CORR_ENA;_160D <= RES_160;_M160 <= (NOT RES_160D) AND RES_160;IF;_H <= COUNT_H1P;RISING_EDGE (CLK_160)THEN_H4 <= COUNT_H + ((3*corr_depth)/4);_H3 <= COUNT_H + ((2*corr_depth)/4);_H2 <= COUNT_H + (corr_depth/4);_H1 <= COUNT_H + 0;RES_160 = 1 THEN_H1P <= 0;(CORR_ENA = 1 and mult_ENA = 1) THEN_H1P <= COUNT_H1P + 1;IF;IF;RISING_EDGE (CLK_160)THENMS_M160(1) = 1 THEN<= 0;(CORR_ENA = 1) THEN<= timer + 1;IF;IF;process;(CLK_160) -- out enablingRISING_EDGE (CLK_160)THENtimer = 0 THEN_o <= 1;timer = (corr_depth/4) THEN_o <= 0;en_o <= en_o;IF;IF;process;_en <= en_o;Behavioral;
Приложение Б - программный код модуля mem_drv
IEEE;IEEE.STD_LOGIC_1164.ALL;IEEE.NUMERIC_STD.ALL;IEEE.STD_LOGIC_SIGNED.ALL;mem_drv is
(corr_depth : natural := 256;_SIZE_CD : natural := 6
);(in_C : IN STD_LOGIC_VECTOR (W_SIZE_CD-1 downto 0);_D : IN STD_LOGIC_VECTOR (W_SIZE_CD-1 downto 0);_ENA : IN STD_LOGIC;_ROM : OUT INTEGER RANGE 0 to 255;_RAM1 : OUT INTEGER RANGE 0 to 127;_RAM2 : OUT INTEGER RANGE 0 to 127;_RAM3 : OUT INTEGER RANGE 0 to 127;_RAM4 : OUT INTEGER RANGE 0 to 127;_RAM_1 : OUT STD_LOGIC;: IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);: IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);: IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);: IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);_160 : IN STD_LOGIC;: OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);: OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);: OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);: OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);_RAM1 : IN INTEGER RANGE 0 to 63;_RAM_2 : OUT STD_LOGIC;_IN : OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0)
);mem_drv;Behavioral of mem_drv isIWE_RAM_1: STD_LOGIC;IWE_RAM_2: STD_LOGIC;NCORR: STD_LOGIC;RWR: STD_LOGIC;DRWR: STD_LOGIC;DDRWR: STD_LOGIC;RW_EN: STD_LOGIC;DNCORR: STD_LOGIC;DDNCORR: STD_LOGIC;CORR: STD_LOGIC;COUNT: INTEGER RANGE 0 TO corr_depth;DCOUNT: INTEGER RANGE 0 TO corr_depth;DDCOUNT: INTEGER RANGE 0 TO (corr_depth/2)-1; ADRR_RAM1 <= AD_RAM1;_RAM2 <= AD_RAM1+64;_RAM3 <= AD_RAM1;_RAM4 <= AD_RAM1+64;
------------------ ADRR_RAM1 <= DDCOUNT;_RAM2 <= 0;_RAM3 <= DDCOUNT;_RAM4 <= 0;
------------------_RAM1 <= 0;_RAM2 <= 0;_RAM3 <= 0;_RAM4 <= 0;
------------------ ADRR_ROM <= 0;case;process;
- CD1 <= INCD1;
- CD2 <= INCD2;
- CD3 <= INCD3;
- CD4 = 127 and RWR = 1_RAM_1 <= 0;_RAM_2 <= 1;_RAM_1 <= 0;_RAM_2 <= 0;IF;<= COUNT;<= DCOUNT;<= NCORR;<= DNCORR;<= (NOT DDNCORR) AND DNCORR;IF;process;
-(CLK_160) beginRISING_EDGE (CLK_160)THENCORR = 1 THEN<= 1;= 255<= 0;RWR <= RWR;IF;IF;process;(CLK_160) -- counterRISING_EDGE (CLK_160)THENCORR = 1 THEN<= 0;(RWR = 1) THEN<= COUNT + 1;<= COUNT;IF;IF;process;Behavioral;